"DESIGN Of HYBRID LOGIC 4-bit COMPARATOR With EFFICIENT VLSI DESIGN CONSTRAINTS"

Authors

Bhaskara Rao Doddi (Assoc. Professor)
Raghu Engineering College, (Autonomous), Visakhapatnam, India.

Kasi Geethanjali & Sekhara Babu Palli (Asst. Professor)
Raghu Engineering College, (Autonomous), Visakhapatnam, India.

Abstract

In this paper, hybrid XOR logic is proposed to design the equality circuit. Hybrid BWIN cell is designed for knowing the status of each bit. Three levels of logic is needed to design the comparator, But with internal hardware optimized at those levels. CMOS logic is also employed for certain portion of the logic. Inverted logic is used for designing XOR, BWIN cell. In this paper the proposed comparator has been designed by using 0. 25 um implementation technology and the tool being used is Tanner tool. It has been reported that 33.5 % reduction in power was seen for the proposed design with the conventional one. 25.5% improvement in the Delay was also achieved for the proposed design when compared to the conventional design. 21% of the area benefit was there for the proposed in comparison to the existing. Power delay product has reported 55.5% efficiency for the proposed one in comparison.